124 size_t dma_buffer_size = (buffer_size * 8) + (2 * 64);
128 if (this->
buf_ ==
nullptr) {
129 ESP_LOGE(TAG,
"Cannot allocate LED buffer!");
136 ESP_LOGE(TAG,
"Cannot allocate effect data!");
143 ESP_LOGE(TAG,
"Cannot allocate DMA buffer!");
148 memset(this->
buf_, 0, buffer_size);
150 memset(this->
dma_buf_, 0, dma_buffer_size);
153 sddev_control(ICU_DEV_NAME, CMD_CONF_PCLK_26M, &value);
155 value = PWD_SPI_CLK_BIT;
156 sddev_control(ICU_DEV_NAME, CMD_CLK_PWR_UP, &value);
158 if (spi_data !=
nullptr) {
159 ESP_LOGE(TAG,
"SPI device already initialized!");
164 spi_data = (spi_data_t *) calloc(1,
sizeof(spi_data_t));
165 if (spi_data ==
nullptr) {
166 ESP_LOGE(TAG,
"Cannot allocate spi_data!");
171 spi_data->dma_tx_semaphore = xSemaphoreCreateBinary();
172 if (spi_data->dma_tx_semaphore ==
nullptr) {
173 ESP_LOGE(TAG,
"TX Semaphore init faild!");
178 spi_data->first_run =
true;
180 set_spi_ctrl_register(MSTEN, 0);
181 set_spi_ctrl_register(BIT_WDTH, 0);
183 set_spi_ctrl_register(CKPOL, 0);
184 set_spi_ctrl_register(CKPHA, 0);
185 set_spi_ctrl_register(MSTEN, 1);
186 set_spi_ctrl_register(SPIEN, 1);
188 set_spi_ctrl_register(TXINT_EN, 0);
189 set_spi_ctrl_register(RXINT_EN, 0);
190 set_spi_config_register(SPI_TX_FINISH_EN, 1);
191 set_spi_config_register(SPI_RX_FINISH_EN, 1);
192 set_spi_ctrl_register(RXOVR_EN, 0);
193 set_spi_ctrl_register(TXOVR_EN, 0);
195 value = REG_READ(SPI_CTRL);
196 value &= ~CTRL_NSSMD_3;
198 REG_WRITE(SPI_CTRL, value);
200 value = GFUNC_MODE_SPI_DMA;
201 sddev_control(GPIO_DEV_NAME, CMD_GPIO_ENABLE_SECOND, &value);
202 set_spi_ctrl_register(SPI_S_CS_UP_INT_EN, 0);
205 GDMACFG_TPYES_ST init_cfg;
206 memset(&init_cfg, 0,
sizeof(GDMACFG_TPYES_ST));
208 init_cfg.dstdat_width = 8;
209 init_cfg.srcdat_width = 32;
210 init_cfg.dstptr_incr = 0;
211 init_cfg.srcptr_incr = 1;
212 init_cfg.src_start_addr = this->
dma_buf_;
213 init_cfg.dst_start_addr = (
void *) SPI_DAT;
214 init_cfg.channel = SPI_TX_DMA_CHANNEL;
216 init_cfg.u.type4.src_loop_start_addr = this->
dma_buf_;
217 init_cfg.u.type4.src_loop_end_addr = this->
dma_buf_ + dma_buffer_size;
218 init_cfg.half_fin_handler =
nullptr;
220 init_cfg.src_module = GDMA_X_SRC_DTCM_RD_REQ;
221 init_cfg.dst_module = GDMA_X_DST_GSPI_TX_REQ;
222 sddev_control(GDMA_DEV_NAME, CMD_GDMA_CFG_TYPE4, (
void *) &init_cfg);
223 en_cfg.channel = SPI_TX_DMA_CHANNEL;
224 en_cfg.param = dma_buffer_size;
225 sddev_control(GDMA_DEV_NAME, CMD_GDMA_SET_TRANS_LENGTH, (
void *) &en_cfg);
226 en_cfg.channel = SPI_TX_DMA_CHANNEL;
228 sddev_control(GDMA_DEV_NAME, CMD_GDMA_CFG_WORK_MODE, (
void *) &en_cfg);
229 en_cfg.channel = SPI_TX_DMA_CHANNEL;
231 sddev_control(GDMA_DEV_NAME, CMD_GDMA_CFG_SRCADDR_LOOP, &en_cfg);
235 value = REG_READ(SPI_CONFIG);
236 value &= ~(0xFFF << 8);
237 value |= ((dma_buffer_size & 0xFFF) << 8);
238 REG_WRITE(SPI_CONFIG, value);