ESPHome 2026.6.0-dev
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wk_reg_def.h
Go to the documentation of this file.
1
5#pragma once
6
7namespace esphome::weikai {
8
12
18
31constexpr uint8_t WKREG_GENA = 0x00;
33constexpr uint8_t GENA_C4EN = 1 << 3;
35constexpr uint8_t GENA_C3EN = 1 << 2;
37constexpr uint8_t GENA_C2EN = 1 << 1;
39constexpr uint8_t GENA_C1EN = 1 << 0;
40
53constexpr uint8_t WKREG_GRST = 0x01;
55constexpr uint8_t GRST_C4RST = 1 << 3;
57constexpr uint8_t GRST_C3RST = 1 << 2;
59constexpr uint8_t GRST_C2RST = 1 << 1;
61constexpr uint8_t GRST_C1RST = 1 << 0;
62
64constexpr uint8_t WKREG_GMUT = 0x02;
65
67constexpr uint8_t WKREG_GIER = 0x10;
68
70constexpr uint8_t WKREG_GIFR = 0x11;
71
84constexpr uint8_t WKREG_GPDIR = 0x21;
85
98constexpr uint8_t WKREG_GPDAT = 0x31;
99
107
113
126constexpr uint8_t WKREG_SPAGE = 0x03;
127
140constexpr uint8_t WKREG_SCR = 0x04;
142constexpr uint8_t SCR_TXEN = 1 << 1;
144constexpr uint8_t SCR_RXEN = 1 << 0;
145
158constexpr uint8_t WKREG_LCR = 0x05;
160constexpr uint8_t LCR_PAEN = 1 << 3;
162constexpr uint8_t LCR_PAR_F0 = 0 << 1;
164constexpr uint8_t LCR_PAR_ODD = 1 << 1;
166constexpr uint8_t LCR_PAR_EVEN = 2 << 1;
168constexpr uint8_t LCR_PAR_F1 = 3 << 1;
170constexpr uint8_t LCR_STPL = 1 << 0;
171
184constexpr uint8_t WKREG_FCR = 0x06;
186constexpr uint8_t FCR_TFEN = 1 << 3;
188constexpr uint8_t FCR_RFEN = 1 << 2;
190constexpr uint8_t FCR_TFRST = 1 << 1;
192constexpr uint8_t FCR_RFRST = 1 << 0;
193
195constexpr uint8_t WKREG_SIER = 0x07;
196
198constexpr uint8_t WKREG_SIFR = 0x08;
199
208constexpr uint8_t WKREG_TFCNT = 0x09;
209
218constexpr uint8_t WKREG_RFCNT = 0x0A;
219
240constexpr uint8_t WKREG_FSR = 0x0B;
242constexpr uint8_t FSR_RFOE = 1 << 7;
244constexpr uint8_t FSR_RFLB = 1 << 6;
246constexpr uint8_t FSR_RFFE = 1 << 5;
248constexpr uint8_t FSR_RFPE = 1 << 4;
250constexpr uint8_t FSR_RFDAT = 1 << 3;
252constexpr uint8_t FSR_TFDAT = 1 << 2;
254constexpr uint8_t FSR_TFFULL = 1 << 1;
256constexpr uint8_t FSR_TBUSY = 1 << 0;
257
259constexpr uint8_t WKREG_LSR = 0x0C;
260
262constexpr uint8_t WKREG_FDAT = 0x0D;
263
270
279constexpr uint8_t WKREG_BRH = 0x04;
280
289constexpr uint8_t WKREG_BRL = 0x05;
290
292constexpr uint8_t WKREG_BRD = 0x06;
293
295constexpr uint8_t WKREG_RFI = 0x07;
296
298constexpr uint8_t WKREG_TFI = 0x08;
299
302} // namespace esphome::weikai
constexpr uint8_t FSR_TFDAT
Transmitter FIFO count (0: empty, 1: not empty)
Definition wk_reg_def.h:252
constexpr uint8_t FCR_RFRST
Receiver FIFO reset.
Definition wk_reg_def.h:192
constexpr uint8_t WKREG_SIFR
Serial Interrupt Flag Register (not used) - c0/c1 1000.
Definition wk_reg_def.h:198
constexpr uint8_t FSR_RFPE
Receiver Parity Error (0: no PE, 1: PE)
Definition wk_reg_def.h:248
constexpr uint8_t FSR_TBUSY
Transmitter busy (0 nothing to transmit, 1: transmitter busy sending)
Definition wk_reg_def.h:256
constexpr uint8_t WKREG_RFCNT
Receiver FIFO count - c0/c1 1010.
Definition wk_reg_def.h:218
constexpr uint8_t SCR_RXEN
receiving control (0: enable, 1: disable)
Definition wk_reg_def.h:144
constexpr uint8_t WKREG_SIER
Serial Interrupt Enable Register (not used) - c0/c1 0111.
Definition wk_reg_def.h:195
constexpr uint8_t WKREG_FCR
FIFO Control Register - c0/c1 0110.
Definition wk_reg_def.h:184
constexpr uint8_t LCR_STPL
Stop length (0: 1 bit, 1: 2 bits)
Definition wk_reg_def.h:170
constexpr uint8_t WKREG_LSR
Line Status Register (not used - using FIFO)
Definition wk_reg_def.h:259
constexpr uint8_t LCR_PAR_F0
Parity force 0.
Definition wk_reg_def.h:162
constexpr uint8_t FCR_TFRST
Transmitter FIFO reset.
Definition wk_reg_def.h:190
constexpr uint8_t SCR_TXEN
transmission control (0: enable, 1: disable)
Definition wk_reg_def.h:142
constexpr uint8_t FCR_TFEN
Transmitter FIFO enable.
Definition wk_reg_def.h:186
constexpr uint8_t FSR_RFOE
Receiver FIFO Overflow Error (0: no OE, 1: OE)
Definition wk_reg_def.h:242
constexpr uint8_t WKREG_FSR
FIFO Status Register - c0/c1 1011.
Definition wk_reg_def.h:240
constexpr uint8_t FCR_RFEN
Receiver FIFO enable.
Definition wk_reg_def.h:188
constexpr uint8_t FSR_RFFE
Receiver FIFO Frame Error (0: no FE, 1: FE)
Definition wk_reg_def.h:246
constexpr uint8_t LCR_PAR_ODD
Parity odd.
Definition wk_reg_def.h:164
constexpr uint8_t FSR_RFDAT
Receiver FIFO count (0: empty, 1: not empty)
Definition wk_reg_def.h:250
constexpr uint8_t WKREG_TFCNT
Transmitter FIFO Count - c0/c1 1001.
Definition wk_reg_def.h:208
constexpr uint8_t FSR_TFFULL
Transmitter FIFO full (0: not full, 1: full)
Definition wk_reg_def.h:254
constexpr uint8_t WKREG_LCR
Line Configuration Register - c0/c1 0101.
Definition wk_reg_def.h:158
constexpr uint8_t WKREG_SCR
Serial Control Register - c0/c1 0100.
Definition wk_reg_def.h:140
constexpr uint8_t FSR_RFLB
Receiver FIFO Line Break (0: no LB, 1: LB)
Definition wk_reg_def.h:244
constexpr uint8_t WKREG_FDAT
FIFO Data Register (not used - does not seems to work)
Definition wk_reg_def.h:262
constexpr uint8_t LCR_PAR_F1
Parity force 1.
Definition wk_reg_def.h:168
constexpr uint8_t LCR_PAR_EVEN
Parity even.
Definition wk_reg_def.h:166
constexpr uint8_t LCR_PAEN
Parity enable (0: no check, 1: check)
Definition wk_reg_def.h:160
constexpr uint8_t WKREG_SPAGE
Global Page register c0/c1 0011.
Definition wk_reg_def.h:126
constexpr uint8_t WKREG_TFI
Transmit FIFO interrupt trigger configuration (not used) - c0/c1 1000.
Definition wk_reg_def.h:298
constexpr uint8_t WKREG_BRH
Baud rate configuration register: high byte - c0/c1 0100.
Definition wk_reg_def.h:279
constexpr uint8_t WKREG_BRL
Baud rate configuration register: low byte - c0/c1 0101.
Definition wk_reg_def.h:289
constexpr uint8_t WKREG_RFI
Receive FIFO Interrupt trigger configuration (not used) - c0/c1 0111.
Definition wk_reg_def.h:295
constexpr uint8_t WKREG_BRD
Baud rate configuration register decimal part - c0/c1 0110.
Definition wk_reg_def.h:292
constexpr uint8_t GRST_C4RST
Channel 4 soft reset (0: not reset, 1: reset)
Definition wk_reg_def.h:55
constexpr uint8_t WKREG_GPDIR
Global GPIO direction register - 10 0001.
Definition wk_reg_def.h:84
constexpr uint8_t WKREG_GPDAT
Global GPIO data register - 11 0001.
Definition wk_reg_def.h:98
constexpr uint8_t WKREG_GIER
Global interrupt register (not used) - 01 0000.
Definition wk_reg_def.h:67
constexpr uint8_t GRST_C2RST
Channel 2 soft reset (0: not reset, 1: reset)
Definition wk_reg_def.h:59
constexpr uint8_t WKREG_GMUT
Global Master channel control register (not used) - 000010.
Definition wk_reg_def.h:64
constexpr uint8_t WKREG_GRST
Global Reset Register - 00 0001.
Definition wk_reg_def.h:53
constexpr uint8_t GRST_C3RST
Channel 3 soft reset (0: not reset, 1: reset)
Definition wk_reg_def.h:57
constexpr uint8_t GENA_C2EN
Channel 2 enable clock (0: disable, 1: enable)
Definition wk_reg_def.h:37
constexpr uint8_t GRST_C1RST
Channel 1 soft reset (0: not reset, 1: reset)
Definition wk_reg_def.h:61
constexpr uint8_t GENA_C3EN
Channel 3 enable clock (0: disable, 1: enable)
Definition wk_reg_def.h:35
constexpr uint8_t GENA_C4EN
Channel 4 enable clock (0: disable, 1: enable)
Definition wk_reg_def.h:33
constexpr uint8_t WKREG_GENA
Global Control Register - 00 0000.
Definition wk_reg_def.h:31
constexpr uint8_t WKREG_GIFR
Global interrupt flag register (not used) 01 0001.
Definition wk_reg_def.h:70
constexpr uint8_t GENA_C1EN
Channel 1 enable clock (0: disable, 1: enable)
Definition wk_reg_def.h:39
When the TEST_COMPONENT flag is defined we include some auto-test methods.
Definition weikai.cpp:9